Writing data, erasing data and reading data to and from memory cells can introduce noise into the process which will result in errors in the data read from the memory cells. To ensure that the data is error free following a read operation, error correction techniques are employed. For example, error correction codes (ECC) are used to encode the data before it is written to the memory cells and then the encoded data are decoded following the read operation. Codes used to correct more than one error in data are, for example, Reed-Solomon and Bose-Chaudhuri-Hochquenghem (BCH). These codes have limited error correction capability when the number of errors increases. This has presented a problem.
A variety of semiconductor manufacturing techniques and circuit designs are used to make memory cells. NAND and NOR flash memory are used in a wide variety of applications that require memory cells. The desire for denser and denser memory cell structures (to increase storage capacity) drives feature size reduction during memory cell development. In addition, memory cells which can store more than a single bit of information are increasingly used, i.e., a multi-level cell (MLC and TLC). In the case of NAND flash memory, a MOSFET is made with a floating gate transistor as a component of a memory cell. During a write operation, a certain amount of charge is injected into the floating gate, placing the floating gate at a specific voltage. The floating gate affects the electric field from the control gate, which modifies the threshold voltage of the cell. If the threshold voltage is not stable over time, errors can occur during read operations. Voltage fluctuations (noise) on the power rails can also contribute to errors. This can present a problem.
Error correction solutions, even when implemented in a combination of hardware and software, often require specific hardware that is designed for the particular error correcting solution selected. Hardware constraints such as this, limit the flexibility of a design. A new design and new hardware are needed when the design criteria (use case) changes. For example, some designs require minimum memory access times, while other designs require a minimum of space on the chip devoted to the error correction function. Resources (time and money) must be expended to implement a new error correction solution for each use case or to include separate on chip hardware for multiple use cases in a single memory controller. This can present a problem.
Various mechanisms create damage to the memory cells, which accumulates over time as the number of program/erase cycles increases. In the case of NAND flash memory, program/ease cycles can cause damage to the tunnel oxide of the floating gate which results in a shift of the threshold voltage of the memory cell. Additionally, the threshold voltage shift of one memory cell can influence the threshold voltage of its neighboring cells through parasitic capacitive-coupling effects, referred to as cell-to-cell interference. These effects which change the value of the data read from the cell relative to what was written are referred to as errors. If the number of read errors increases as the device ages, beyond that which can be corrected by the ECC, the integrity of the data is lost. All of this presents a host of problems.